SPIM Instruction Set

This document gives an overview of the more common instructions used in the SPIM simulator. See Appendix A of Computer Organization and Design by Hennessy and Patterson for more details.

Overview

The SPIM simulator implements the full MIPS instruction set, as well as a large number of pseudoinstructions that correspond to one or more equivalent MIPS instructions. There are also a small number of system call commands used to interface with the console window of the SPIM simulator. Finally, SPIM renames registers according to commonly used conventions in order to facilitate the readability of programs.

Instructions and PseudoInstructions

The following is an abbreviated list of MIPS instructions and SPIM pseudoinstructions. This list is not complete. Notably missing are all Floating Point and coprocessor instructions.

• - Indicates an actual MIPS instruction. Others are SPIM pseudoinstructions.

Instruction Function

• add Rd, Rs, Rt Rd = Rs + Rt (signed)

• addu Rd, Rs, Rt Rd = Rs + Rt (unsigned)

• addi Rd, Rs, Imm Rd = Rs + Imm (signed)

• sub Rd, Rs, Rt Rd = Rs - Rt (signed)

• subu Rd, Rs, Rt Rd = Rs - Rt (unsigned)

• div Rs, Rt lo = Rs/Rt, hi = Rs mod Rt (integer division, signed)

• divu Rs, Rt lo = Rs/Rt, hi = Rs mod Rt (integer division, unsigned)

div Rd, Rs, Rt Rd = Rs/Rt (integer division, signed)

divu Rd, Rs, Rt Rd = Rs/Rt (integer division, unsigned)

rem Rd, Rs, Rt Rd = Rs mod Rt (signed)

remu Rd, Rs, Rt Rd = Rs mod Rt (unsigned)

mul Rd, Rs, Rt Rd = Rs * Rt (signed)

• mult Rs, Rt hi, lo = Rs * Rt (signed, hi = high 32 bits, lo = low 32 bits)

• multu Rd, Rs hi, lo = Rs * Rt (unsigned, hi = high 32 bits, lo = low 32 bits)

• and Rd, Rs, Rt Rd = Rs • Rt

• andi Rd, Rs, Imm Rd = Rs • Imm

neg Rd, Rs Rd = -(Rs)

• nor Rd, Rs, Rt Rd = (Rs + Rt)’

not Rd, Rs Rd = (Rs)’

• or Rd, Rs, Rt Rd = Rs + Rt

• ori Rd, Rs, Imm Rd = Rs + Imm

• xor Rd, Rs, Rt Rd = Rs ⊕ Rt

• xori Rd, Rs, Imm Rd = Rs ⊕ Imm

• sll Rd, Rt, Sa Rd = Rt left shifted by Sa bits

• sllv Rd, Rs, Rt Rd = Rt left shifted by Rs bits

• srl Rd, Rs, Sa Rd = Rt right shifted by Sa bits

• srlv Rd, Rs, Rt Rd = Rt right shifted by Rs bits

move Rd, Rs Rd = Rs

• mfhi Rd Rd = hi

• mflo Rd Rd = lo

li Rd, Imm Rd = Imm

• lui Rt, Imm Rt[31:16] = Imm, Rt[15:0] = 0

• lb Rt, Address(Rs) Rt = byte at M[Address + Rs] (sign extended)

• sb Rt, Address(Rs) Byte at M[Address + Rs] = Rt (sign extended)

• lw Rt, Address(Rs) Rt = word at M[Address + Rs]

• sw Rt, Address(Rs) Word at M[Address + Rs] = Rt

• slt Rd, Rs, Rt Rd = 1 if Rs < Rt, Rd = 0 if Rs ≥ Rt (signed)

• slti Rd, Rs, Imm Rd = 1 if Rs < Imm, Rd = 0 if Rs ≥ Imm (signed)

• sltu Rd, Rs, Rt Rd = 1 if Rs < Rt, Rd = 0 if Rs ≥ Rt (unsigned)

• beq Rs, Rt, Label Branch to Label if Rs == Rt

beqz Rs, Label Branch to Label if Rs == 0

bge Rs, Rt, Label Branch to Label if Rs ≥ Rt (signed)

• bgez Rs, Label Branch to Label if Rs ≥ 0 (signed)

• bgezal Rs, Label Branch to Label and Link if Rs ≥ Rt (signed)

bgt Rs, Rt, Label Branch to Label if Rs > Rt (signed)

bgtu Rs, Rt, Label Branch to Label if Rs > Rt (unsigned)

• bgtz Rs, Label Branch to Label if Rs > 0 (signed)

ble Rs, Rt, Label Branch to Label if Rs ≤ Rt (signed)

bleu Rs, Rt, Label Branch to Label if Rs ≤ Rt (unsigned)

• blez Rs, Label Branch to Label if Rs ≤ 0 (signed)

• bgezal Rs, Label Branch to Label and Link if Rs ≥ 0 (signed)

• bltzal Rs, Label Branch to Label and Link if Rs < 0 (signed)

blt Rs, Rt, Label Branch to Label if Rs < Rt (signed)

bltu Rs, Rt, Label Branch to Label if Rs < Rt (unsigned)

• bltz Rs, Label Branch to Label if Rs < 0 (signed)

• bne Rs, Rt, Label Branch to Label if Rs ≠ Rt

bnez Rs, Label Branch to Label if Rs ≠ 0

• j Label Jump to Label unconditionally

• jal Label Jump to Label and link unconditionally

• jr Rs Jump to location in Rs unconditionally

• jalr Label Jump to location in Rs and link unconditionally